The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
A transistor device may be strained—for example through application of a stress—to improve carrier mobility in its conductive channel. The stress may be provided by source/drain stressors formed adjacent to the channel. However, depending on the location of the source/drain stressor relative to a free boundary (e.g., shallow trench isolation), the stress provided by the source/drain stressor may be substantially reduced, thereby degrading carrier mobility. Conventional strained transistor devices have not provided a good solution to this problem. Therefore, while existing strained transistor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.